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Author Topic: PowerPC 600 - overview : wikipedia  (Read 1473 times)

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Offline chrisNova777

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PowerPC 600 - overview : wikipedia
« on: September 13, 2014, 03:58:54 AM »
http://en.wikipedia.org/wiki/PowerPC_600

Quote
The PowerPC 600 family was the first family of PowerPC processors built. They were designed at the Somerset facility in Austin, Texas, jointly funded and staffed by engineers from IBM and Motorola as a part of the AIM alliance. Somerset was opened in 1992 and its goal was to make the first PowerPC processor and then keep designing general purpose PowerPC processors for personal computers. The first incarnation became the PowerPC 601 in 1993, and the second generation soon followed with the PowerPC 603, PowerPC 604 and the 64-bit PowerPC 620.

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The PowerPC 601 was the first generation of microprocessors to support the basic 32-bit PowerPC instruction set. The design effort started in earnest in mid-1991 and the first prototype chips were available in October 1992.

The first 601 processors were introduced in an IBM RS/6000 workstation in October 1993 (alongside its more powerful multichip cousin IBM POWER2 line of processors) and the first Apple Power Macintoshes on March 14, 1994. The 601 was the first advanced single-chip implementation of the POWER/PowerPC architecture designed on a crash schedule to establish PowerPC in the marketplace and cement the AIM alliance.

In order to achieve an extremely aggressive schedule while including substantially new function (such as substantial performance enhancements, new instructions and importantly POWER/PowerPC's first symmetric multiprocessing (SMP) implementation) the design leveraged a number of key technologies and project management strategies. The 601 team leveraged much of the basic structure and portions of the IBM RISC Single Chip (RSC) processor, but also included support for the vast majority of the new PowerPC instructions not in the POWER instruction set.

While nearly every portion of the RSC design was modified, and many design blocks were substantially modified or completely redesigned given the completely different unified I/O bus structure and SMP/memory coherency support. New PowerPC changes, leveraging the basic RSC structure was very beneficial to reducing the uncertainty in chip area/floorplanning and timing analysis/tuning.

Worth noting is that the 601 not only implemented substantial new key functions such as SMP, but it also acted as a bridge between the POWER and the future PowerPC processors to assist IBM and software developers in their transitions to PowerPC. From start of design to tape-out of the first 601 prototype was just 12 months in order to push hard to establish PowerPC on the market early.